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Newsletter

Untitled Document
A periodic newsletter for the NSF Science and Technology Center on
Materials and Devices for Information Technology Research

TABLE OF CONTENTS

New Fabrication Scheme

Future Tech Conference

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CMDITR Video Clip

Welcome Denise Wilson
& Deborah Illman


RCR Made Public

Travel Report:
Susan Odom


Recent Publications

CMDITR Handbook Available


September/October 2005
PAGE 1 | 2 | 3 | 4 |

New Fabrication Scheme in the Chen Research Group

By Susan Soggs

The large radio-frequency bandwidths and low switching voltages of electro-optic (EO) polymer devices are making them a viable alternative to current crystalline-based technologies for high-speed telecommunications applications. In addition, since metal oxide semiconductor (MOS) transistor circuits and EO polymer devices use compatible processes they can be fabricated in the same clean-room facility and even on the same silicon wafer. This same-substrate integration has the potential benefit of streamlined operation as well as reduced manufacturing and packaging costs.

The usual design of same-substrate integration schemes is often adversely affected by competing device requirements. The process required to achieve the desired qualities or behaviors in the EO polymer can compromise MOS integrity. For example, a thin film composed of randomized chromophore “guest” molecules in a polymer “host” matrix must undergo a high-field poling process which aligns the chromophores in order to instill EO behavior in the overall thin film (Figure 2). However, application of high electric fields is known to compromise MOS thin gate oxide integrity. On the other hand, polymers cannot withstand high temperature (>700oC) MOS fabrication processes.

In order to address these issues the Chen Research Group developed a two-step fabrication scheme. An EO polymer device was fabricated over a thick flexible polymer layer on one Si substrate, poled, removed, then adhered over MOS amplifier circuitry fabricated on a second substrate (Figures 3 and 4). This lift-off scheme is adapted from literature with the addition of electrical interconnects that allow the MOS circuit to control the EO device. Thus, MOS devices were not subjected to EO polymer poling fields, and EO polymers were not subjected to the MOS device processing temperatures.

Test results are shown below in Figure 5. The top trace is the function generator input to integrated device, while the next trace is the amplified and inverted output of the MOS amplifier circuit. The bottom trace is the detected output of the EO polymer modulator as driven by the MOS circuit. These results demonstrate the success of this lift-off integration technique.

Chromophore Alignment to instill EO activity
Figure 2
Chromophore Alignment to instill EO activity

EO polymer device fabrication and lift-off
Figure 3
EO polymer device fabrication and lift-off

EO polymer over MOS device
Figure 4
EO polymer over MOS device

Integrated Device Electrical Results
Figure 5
Integrated Device Electrical Results

This material is based upon work supported by the STC Program of the National Science Foundation No. DMR 0120967. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.
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